1. Technical Field
The present disclosure relates to a method of fabricating a semiconductor device, and more particularly, to a method of forming a semiconductor device with a dielectric layer having an air gap to isolate wirings or a gate stack of the semiconductor device.
2. Description of the Related Art
As semiconductor devices such as logic elements, DRAMs, or flash memories are typically highly integrated, the distance between metal wirings in the semiconductor devices may gradually decrease. Capacitive coupling due to a parasitic capacitance generated by the metal wirings and a dielectric layer for isolating the metal wirings may cause an interconnection delay that hinders the integration and high speed of a semiconductor device.
In addition to the interconnection delay, signal interference due to the capacitive coupling may be generated between gate stacks of neighboring cells of a flash memory device. For example, in a flash memory device, during programming or a read operation of a selected flash memory cell, the programming or read operation may fail due to the capacitive coupling of the selected flash memory cell with an unselected flash memory cell.
To reduce the capacitive coupling due to the parasitic capacitance generated between the neighboring metal wirings or memory cells, technologies that involve using of a material having a low dielectric capacitance for the dielectric layer or forming an air gap or void in the dielectric layer, are used. In particular, as the air gap may provide a dielectric capacitance of about 1.0, the capacitive coupling can be effectively reduced. However, the above method of forming the dielectric layer of a material having a low dielectric capacitance or with the air gap may be required to avoid deteriorating or damaging the electrical characteristics of constituent elements, such as, for example, wiring members or gate stacks, that have been already embodied, during the application thereof.